1. Field of the Invention
The invention is generally directed to digital signal processing. The invention is more specifically directed to a method of generating a sequence of address signals for use in a digital signal processing system where the system performs finite impulse response (FIR) or fast Fourier transform (FFT) or other circular-buffer style processing on input data received from a plurality of digitally sampled signal sources.
2a. Cross Reference to Related Applications
The following copending U.S. patent application(s) is/are assigned to the assignee of the present application, is/are related to the present application and its/their disclosures is/are incorporated herein by reference:
(A) Ser. No. 07/877,949 filed Apr. 30, 1992 by Raul Aguilar and Jeffrey Miller and entitled, DIGIT REVERSE FOR MIXED RADIX FFT; and PA1 (B) Ser. No. 07/877,317 filed May 1, 1992 by Michael E. Fleming and entitled, MULTI-PORT DIGITAL SIGNAL PROCESSOR. PA1 2b. Cross Reference to Related Patents PA1 (A) U.S. Pat. No. 4,908,748 issued Mar. 13, 1990 to B. Pathak, et al, and entitled, DATA PROCESSING DEVICE WITH PARALLEL CIRCULAR ADDRESS HARDWARE; and PA1 (B) U.S. Pat. No. 5,032,986 issued Jul. 16, 1991 to B. Pathak, et al, and entitled, DATA PROCESSING DEVICE WITH PARALLEL CIRCULAR ADDRESS HARDWARE.
The following U.S. patent(s) is/are related to the present application and its/their disclosures is/are incorporated herein by reference:
3. Description of the Related Art
A classic approach in digital signal processing (DSP) uses tapped delay lines with weighted outputs to perform real-time finite-impulse-response (FIR) filtering. Digitized sample data enters a front end of the tapped delay line, one new data item per clock cycle, while earlier received, and thus older, data items shift serially towards the back of the line. A summing means is provided for adding together the weighted outputs of the tapped delay line. A filtered version of the input signal stream develops at the output of the summing means over time. Different FIR filtering schemes call for different lengths of delay and different sets of weighting coefficients.
In the early days of DSP technology, a chain of series-connected synchronous shift registers was used to define the delay line. Digital multipliers were attached to the delay line, typically allotting one multiplier for each shift register, and used to multiply the outputs of the shift registers by corresponding weighting-coefficients. The maximum amount of delay which could be applied to any given item of new input data was defined by the system clock rate and the total number of shift registers in the series chain. This number is sometimes referred to as the "length" of the FIR filter. A digital summing means was also provided for collecting and summing the outputs of the shift registers and/or multipliers.
Modern DSP designs replace the classic chain of series-connected shift registers with a single random access memory unit (RAM). Input data items (sample point values) are written into uniquely addressed locations of the RAM unit when received. They are afterwards read out, as needed, and supplied to a recursively operating weight-and-sum processing unit. The weight-and-sum processing unit multiplies each readout data item by a corresponding weighting coefficient and adds the result to a rolling subtotal. The rolling subtotal corresponds to the output of the classic FIR filter.
A circular-buffer scheme is often used to minimize the amount of storage capacity required in the RAM unit. Old sample values, which are no longer needed, are overwritten by new input data. A circular buffer management system keeps track of which RAM locations hold the newest, still in-use data items, and which RAM locations store the oldest, usually-discardable data items.
Management of circular buffer addressing is relatively trivial in cases where the sample rate of the incoming data is relatively low, say 1000 input items (data words) per second, and a single filter having a fixed filter length equivalent to that of, say 64 shift registers, is being implemented. A general purpose microprocessor operating at a clock speed of 10 MHz or better can be used to perform buffer management calculations and to output an appropriate sequence of address signals for storing and/or fetching sample values into/out-of RAM on a real-time basis.
The general-purpose microprocessor becomes too slow, however, when relatively large numbers of input channels are to be simultaneously processed in real-time by different filters and/or when the combined data sampling rates of the channels exceed the peak processing rate of the microprocessor. This can occur for example when the incoming data arrives from a multi-channel wide-bandwidth communication system, or from a digital video source or from any other high-throughput source.
Recently, a class of high-performance, user-configurable DSP integrated circuit units have been introduced. The Sharp LH9124 is an example. Each LH9124 DSP unit is capable of processing a continuous stream of 48-bit wide input words at rates as high as 40 MHz (4.times.10.sup.6 input words per second), with each 48-bit word being composed for example of a 24-bit real part and a 24-bit imaginary part. This development opens the way for commercially-practical digital processing of real-time signals produced by digital telemetry systems, digital image processing systems, digital radio, digital video, digital speech processing systems, tomography systems, and the like.
Circular buffer address management in such high-speed multi-channel environments remains a problem, however.